Verilog 硬體描述語言: 2014

2014年12月22日星期一

考試1

module top;
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #400 clock1(a);
system_clock #50 clock1(d);
number n1(e,a,b,c,d);
endmodule

module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(w1,a1,b1,c);
and(w2,a,c1);
and(w3,b,c1,d);
and(w4,a,b,d);

or(e,w1,w2,w3,w4);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

module top;
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #400 clock1(a);
system_clock #50 clock1(d);
number n1(e,a,b,c,d);
endmodule

module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5,w6,v1,v2,v3,v4;
nand(a1,a,a);
nand(b1,b,b);
nand(c1,c,c);
nand(d1,d,d);
nand(w1,a1,b1,c);
nand(k1,w1,w1);
nand(w2,a,c1);
nand(k2,w2,w2);
nand(w3,b,c1,d);
nand(k3,w3,w3);
nand(w4,a,b,d);
nand(k4,w4,w4);
nand(v1,k1,k1);
nand(v2,k2,k2);
nand(v3,k3,k3);
nand(v4,k4,k4);

nand(e,v1,v2,v3,v4);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

2014年11月17日星期一

一位元加法器行為模式設計與測試P.29

module test_adder1;

reg a,b;
reg carry_in ;
wire sum;
wire carry_out;

adder1_behavorial A1(carry_out, sum, a, b, carry_in);

initial
begin

carry_in = 0; a = 0; b = 0;
# 100 if ( carry_out !== 0 | sum !== 0)
$display(" 0+0+0=00 sum is WRONG!");
else
$display(" 0+0+0=00 sum is RIGHT!");
carry_in = 0; a = 0; b = 1;
# 100 if ( carry_out !== 0 | sum !== 1)
$display(" 0+0+1=01 sum is WRONG!");
else
$display(" 0+0+1=01 sum is RIGHT!");
carry_in = 0; a = 1; b = 0;
# 100 if ( carry_out !== 0 | sum !== 1)
$display(" 0+1+0=01 sum is WRONG!");
else
$display(" 0+1+0=01 sum is RIGHT!");
carry_in = 0; a = 1; b = 1;
# 100 if ( carry_out !== 1 | sum !== 0)
$display(" 0+1+1=10 sum is WRONG!");
else
$display(" 0+1+1=10 sum is RIGHT!");
carry_in = 1; a = 0; b = 0;
# 100 if ( carry_out !== 0 | sum !== 1)
$display(" 1+0+0=01 sum is WRONG!");
else
$display(" 1+0+0=01 sum is RIGHT!");
carry_in = 1; a = 0; b = 1;
# 100 if ( carry_out !== 1 | sum !== 0)
$display(" 1+0+1=10 sum is WRONG!");
else
$display(" 1+0+1=10 sum is RIGHT!");
carry_in = 1; a = 1; b = 0;
# 100 if ( carry_out !== 1 | sum !== 0)
$display(" 1+1+0=10 sum is WRONG!");
else
$display(" 1+1+0=10 sum is RIGHT!");
carry_in = 1; a = 1; b = 1;
# 100 if ( carry_out !== 1 | sum !== 1)
$display(" 1+1+1=11 sum is WRONG!");
else
$display(" 1+1+1=11 sum is RIGHT!");

$finish;

end
endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);
input a, b, carry_in;
output carry_out, sum;
assign sum = (a^b)^carry_in;
assign carry_out = (a^b)&carry_in|(a&b);
endmodule

一位元加法器行為模式設計與測試

module test_adder1;

reg a,b;
reg carry_in ;
wire sum;
wire carry_out;

adder1_behavorial A1(carry_out, sum, a, b, carry_in);

initial
begin

carry_in = 0; a = 0; b = 0;
# 100 if ( carry_out !== 0 | sum !== 0)
$display(" 0+0+0=00 sum is WRONG!");
else
$display(" 0+0+0=00 sum is RIGHT!");
carry_in = 0; a = 0; b = 1;
# 100 if ( carry_out !== 0 | sum !== 1)
$display(" 0+0+1=01 sum is WRONG!");
else
$display(" 0+0+1=01 sum is RIGHT!");
carry_in = 0; a = 1; b = 0;
# 100 if ( carry_out !== 0 | sum !== 1)
$display(" 0+1+0=01 sum is WRONG!");
else
$display(" 0+1+0=01 sum is RIGHT!");
carry_in = 0; a = 1; b = 1;
# 100 if ( carry_out !== 1 | sum !== 0)
$display(" 0+1+1=10 sum is WRONG!");
else
$display(" 0+1+1=10 sum is RIGHT!");
carry_in = 1; a = 0; b = 0;
# 100 if ( carry_out !== 0 | sum !== 1)
$display(" 1+0+0=01 sum is WRONG!");
else
$display(" 1+0+0=01 sum is RIGHT!");
carry_in = 1; a = 0; b = 1;
# 100 if ( carry_out !== 1 | sum !== 0)
$display(" 1+0+1=10 sum is WRONG!");
else
$display(" 1+0+1=10 sum is RIGHT!");
carry_in = 1; a = 1; b = 0;
# 100 if ( carry_out !== 1 | sum !== 0)
$display(" 1+1+0=10 sum is WRONG!");
else
$display(" 1+1+0=10 sum is RIGHT!");
carry_in = 1; a = 1; b = 1;
# 100 if ( carry_out !== 1 | sum !== 1)
$display(" 1+1+1=11 sum is WRONG!");
else
$display(" 1+1+1=11 sum is RIGHT!");

$finish;

end
endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);
input a, b, carry_in;
output carry_out, sum;
assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule

2014年11月3日星期一

3位元多工器

module top;
wire [2:0] A, B, OUT;
wire SEL;
system_clock #3200 clock1(A[0]);
system_clock #1600 clock2(B[1]);
system_clock #800 clock3(A[2]);
system_clock #400 clock4(B[0]);
system_clock #200 clock3(A[1]);
system_clock #100 clock4(B[2]);

system_clock #50 clock5(SEL);

mux3 M1(OUT,A,B,SEL);

endmodule

module mux3(OUT, A, B, SEL);
output [2:0] OUT;
input [2:0] A,B;
input SEL;
mux hi (OUT[2],A[2],B[2],SEL);
mux lo (OUT[0],A[0],B[0],SEL);
mux middle (OUT[1],A[1],B[1],SEL);
endmodule

module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL) ;
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
begin
#(PERIOD/2) clk=~clk;
end

always@(posedge clk)
if($time>1000)$stop;

endmodule

2014年10月27日星期一

行為模式 2位元多工器

module top;
integer ia0,ia1,ib0,ib1,is;
reg a0,a1,b0,b1,s;
wire out1,out2;

mux_behavioral mux1(out1,out2,a0,a1,b0,b1,s);

initial
begin
for (ia0=0; ia0<=1; ia0 = ia0+1)
begin
a0 = ia0;
for (ia1=0; ia1<=1; ia1 = ia1+ 1)
begin
a1 = ia1;
for (ib0=0; ib0<=1; ib0 = ib0+1)
begin
b0 = ib0;
for (ib1=0; ib1<=1; ib1 = ib1+ 1)
begin
b1 = ib1;
for (is=0; is<=1; is = is + 1)
begin
s = is;
#100 $display("a0=%d a1=%d b0=%d b1=%d s=%d out1=%d out2=%d",a0,a1,b0,b1,s,out1,out2);
end
end
end
end
end
end
endmodule

module mux_behavioral(OUT1,OUT2,A0,A1,B0,B1,SEL);
output OUT1,OUT2;
input A0,A1,B0,B1,SEL;
wire A0,A1,B0,B1,SEL;
reg OUT1,OUT2;

always @(A0 or A1 or B0 or B1 or SEL)
begin
OUT1 = (A0 & SEL)|(B0 & ~SEL );
OUT2 = (A1 & SEL)|(B1 & ~SEL );
end
endmodule