考試1

module top;
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #400 clock1(a);
system_clock #50 clock1(d);
number  n1(e,a,b,c,d);
endmodule

module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(w1,a1,b1,c);
and(w2,a,c1);
and(w3,b,c1,d);
and(w4,a,b,d);

or(e,w1,w2,w3,w4);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule







module top;
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #400 clock1(a);
system_clock #50 clock1(d);
number  n1(e,a,b,c,d);
endmodule

module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4,w5,w6,v1,v2,v3,v4;
nand(a1,a,a);
nand(b1,b,b);
nand(c1,c,c);
nand(d1,d,d);
nand(w1,a1,b1,c);
nand(k1,w1,w1);
nand(w2,a,c1);
nand(k2,w2,w2);
nand(w3,b,c1,d);
nand(k3,w3,w3);
nand(w4,a,b,d);
nand(k4,w4,w4);
nand(v1,k1,k1);
nand(v2,k2,k2);
nand(v3,k3,k3);
nand(v4,k4,k4);

nand(e,v1,v2,v3,v4);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule